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Motor Drivers for Printers
Three-phase Brushless Motor Pre-drivers for Paper Feed
BD6761FS,BD6762FV
No.10016EAT01
Description This product is the motor predriver for high-side/low-side N-channel MOS-FET drive, which has the built-in booster (step-up) circuit. BD6761FS uses the drive type controlled by the servo signal input from outside and BD6762FV incorporates a servo circuit (Speed discriminator + PLL servo). Features 1) Predriver for high-side/low-side N-channel MOS-FET 2) Built-in booster (step-up) circuit 3) Built-in FG and hysteresis amplifiers 4) Built-in current limit circuit 5) Built-in thermal shutdown circuit 6) Built-in forward/reverse rotation switching circuit (BD6761FS, FD6762FV) 7) Built-in short brake circuit (BD6761FS, BD6762FV) 8) Built-in low voltage protection circuit (BD6761FS, BD6762FV) 9) Built-in speed lock detection circuit (BD6762FV) 10) Built-in motor lock protection circuit (BD6762FV) 11) Built-in start-stop circuit (BD6762FV) 12) Built-in servo circuit (Speed discriminator + PLL) (BD6762FV) 13) Built-in frequency multiplication circuit (BD6762FV) 14) 180, direct PWM drive (BD6761FS) 15) 120, slope switchable direct PWM drive (BD6762FV) Applications Main motor for paper feed of the laser beam printer and PPC Absolute Maximum Ratings (Ta=25) Parameter Applied voltage Applied voltage Pin input voltage Power dissipation Operating temperature range Storage temperature range Junction temperature Symbol VCC VG Vin Pd TOPR TSTG Tjmax Ratings BD6761FS 36 36 VREG 950
(1)
BD6762FV 36 36 VREG 1100
(2)
Unit V V V mW
-35 ~ +75 -40 ~ +150 150
-25 ~ +75 -40 ~ +150 150
1 Reduced by 7.6 mW/ over 25, when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm). 2 Reduced by 8.8 mW/ over 25, when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm).
Line up Matrix BD6761FS Power supply voltage (VCC) Drive type Servo 16~28 180 No BD6762FV 16~28 120 / 120 slope Yes Unit V
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1/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Electrical Characteristics BD6761FS (Unless otherwise specified, Ta=25C, VCC=24.0V) Limits Parameter Symbol Min. Typ. Overall Circuit current ICC 10 15 VREG voltage VREG 5.5 6 Hall amp Input bias current IHA 0.7 In-phase input voltage range VHAR 1.5 Input level VINH 30 PWM High CFE voltage VHPCFE 3.0 3.5 Low CFE voltage VLPCFE 2.1 2.5 CFE oscillating frequency FCFE 12 15 PWM on duty offset DPWM -1.5 0 Torque amplifier High CPOUT input current ICPOUTH 0 Low CPOUT input current ICPOUTL -1 0 Current limit Current detection voltage 1 VCL1 0.391 0.435 Current detection voltage 2 VCL2 0.432 0.480 VCL2-VCL1 VCL 40 45 FG Amp Input bias current IBFG -1 Input offset voltage VBFG -10 High output voltage VHFG 4.5 5.0 Low output voltage VLFG 1.0 Low FGS output voltage VLFGS 0.1 Open loop gain GVFG 45 54 Bias voltage VBIASFG 2.7 3.0 Hysteresis width VHYS 100 180 F/R High input current IFRL 30 60 Low input current IFRH -10 0 High input level VIHFR 2.2 Low input level VILFR 0 ACC and DEC High ACC input current IACCH 30 60 Low ACC input current IACCL -10 0 High DEC input current IDECH 30 60 Low DEC input current IDECL -10 0 Accelerating current ISS -260 -200 Decelerating current ISO 140 200 High ACC input level VIHACC 2.2 Low ACC input level VILACC 0 High DEC input level VIHDEC 2.2 Low DEC input level VILDEC 0 High-side output High-side voltage VHG Vcc+5 Vcc+6 Pull-down resistor RHD 70 100 Low-side output Low-side voltage VLG 9.5 10.5 Pull-down resistor RLD 70 100 Booster Boost voltage VG Vcc+5 Vcc+6 CP1 oscillating frequency FCP1 35 62.5
Technical Note
Max. 20 6.5 3.0 4.1 250 4.0 2.9 18 1.5 1 0.479 0.528 50 1 10 VREG 1.5 0.3 3.3 250 90 10 VREG 0.8 90 10 90 10 -140 260 VREG 0.8 VREG 0.8 Vcc+7 130 11.5 130 Vcc+7 85
Unit mA V
Conditions
IVREG=-1mA
A V mVpp Single-phase Hall amplitude V V kHz % A A V V mV A mV V V V dB V mV A A V V A A A A A A V V V V V k V k V kHz For current sense amplifier For current limit comparator
RFE=50k, CFE=1000pF
IHFGOUT=-0.75mA ILFGOUT=2mA ILFGSOUT=3mA f=3kHz
F/R=6V F/R=0V Reverse rotation Forward rotation ACC=6V ACC=0V DEC=6V DEC=0V RCP=13.5k, ACC=L RCP=13.5k, DEC=L
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2/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Technical Note
BD6762FV (Unless otherwise specified, Ta=25C, VCC=24V) Parameter Symbol Min. Limits Typ. Max. 10.2 25 5.5 13.5 0.6 3 3 3.2 1.6 19 1.15 1 10 1.5 0.3 2.75 250 2.7 0.9 2.75 0.3 0.45 0.3 27 2.5 VREG 0.8 10 -60 Unit mA mA V V V A V mVp-p V V kHz V A mV V V V dB V mV V V V V V V V V msec kHz V V A A Conditions ST/SP=OPEN ST/SP=GND IVREG=-1mA
Overall 5.1 7.6 Circuit current 1 ICCS 10 17 Circuit current 2 ICC 4.5 5 VREG voltage VREG 9.5 11.5 Low voltage protection level VUVON 0.4 0.5 Low voltage protection hysteresis level VUVHYS Hall amp 1 Input bias current IBH 0 In-phase input voltage range VHAR 50 Input level VINH PWM 2.6 2.9 High CFE voltage VCFEH 1.2 1.4 Low CFE voltage VCFEL 13 16 CFE oscillating frequency FCFE 0.75 0.95 REF voltage VRFE FG amp -1 Input bias current IFGM -10 Input offset voltage VFGOF 3.5 4.0 High output voltage VFGOH 1.0 Low output voltage VFGOL 0.1 Low FGS output voltage VFGSL 45 54 Open loop gain GFG 2.25 2.50 Bias voltage VBFG 100 180 Hysteresis width VFGHYS Integration amp 1.5 2.1 Di clamp voltage 1 VDI1 0.5 0.7 Di clamp voltage 2 VDI2 2.25 2.50 Bias voltage VBERR Speed discriminator High output voltage VDOH VREG-0.3 VREG-0.1 0.1 Low output voltage VDOL PLL High output voltage VPOH VREG-0.45 VREG-0.15 0.15 Low output voltage VPOL Lock detection 0.15 Low output voltage VLDL Lock protection 13 20 CLK cycle for protection circuit TLP VCO 0.2 CLK input frequency range FCLK 2.2 High-level CLK input voltage VCKH 0 Low-level CLK input voltage VCKL -10 High-level CLK input current ICKH -140 -100 Low-level CLK input current ICKL
RFE=20K, CFE=1000pF
I=-0.5mA I=0.5mA I=2mA f=3kHz
INTIN=0.1mA INTOUT0.1mA INTIN=INTOUT I=-0.1mA I=0.1mA I=-0.1mA I=0.1mA I=2mA LP=0.1F Designed value (VCO alone)
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3/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Technical Note
BD6762FV (Unless otherwise specified, Ta=25C, VCC=24 V) Parameter Start/Stop High-level ST/SP input voltage Low-level ST/SP input voltage High-level ST/SP input current Low-level ST/SP input current Forward rotation/Reverse rotation High-level FR input voltage Low-level FR input voltage High-level FR input current Low-level FR input current 120/Slope switching High-level 120/slope input voltage Low-level 120/slope input voltage High-level 120/slope input current Low-level 120/slope input current Short brake High-level SB input voltage Low-level SB input voltage High-level SB input current Low-level SB input current Current limit Current detection voltage Booster CP1 oscillating frequency VG step-up voltage High-side output High output voltage 1 High output voltage 2 Low output voltage 1 Low output voltage 2 Clamp voltage Low-side output High output voltage 1 High output voltage 2 Low output voltage 1 Low output voltage 2 Symbol VSTH VSTL ISTH ISTL VFRH VFRL IFRH IFRL VANH VANL IANH IANL VSBH VSBL ISBH ISBL VCL FCP1 VG VHHG1 VHHG2 VHLG1 VHLG2 VHCL VLHG1 VLHG2 VLLG1 VLLG2 Min. 2.2 0 -10 -70 2.2 0 -10 -70 2.2 0 -10 -70 2.2 0 -10 -70 0.23 75 VCC+5.7 VCC+5.8 VCC+3.8 10 9.8 9.0 Limits Typ. 0 -50 0 -50 0 -50 0 -50 0.26 125 VCC+6.7 VCC+6.8 VCC+4.8 0.1 0.5 11 10.8 10.0 0.1 0.3 Max. VREG 0.8 10 -30 VREG 0.8 10 -30 VREG 0.8 10 -30 VREG 0.8 10 -30 0.29 175 VCC+7.7 VCC+7.8 VCC+5.8 0.3 1.0 12 11.8 11.0 0.3 0.5 Unit V V A A V V A A V V A A V V A A V kHz V V V V V V V V V V VG=31V Io=-1mA Io=5mA STOP START Conditions
Reverse rotation Forward rotation
120 120 slope
Short brake operation Short brake clear
Io=-5mA Io=5mA
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4/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Reference Data
25 20 7.0 40.0 35.0 6.5
Technical Note
25
-35
VREG[V]
-35
ICC[mA]
25
-35
VG[V]
30.0 25.0 20.0 15.0 10.0 5.0
15 10 5 0 16 21 26 31 36
75
6.0
75
25
5.5
75
5.0 0 2.5 5 7.5 10
0.0 0 1 2 3 4 5
Supply voltage :VCC[V]
VREG current : IVREG[mA]
VG current : IVG[mA]
Fig.1 Circuit current (BD6761FS)
Fig. 2 VREG Voltage (BD6761FS)
Fig. 3 VG Voltage (BD6761FS)
25 20
6.0
40.0 35.0
25
-25
5.5
-25
30.0
75
VG[V]
15 10 5 0 16 21 26
VREG[V]
ICC[mA]
-25
5.0
25.0 20.0 15.0
75
25
4.5
75
25
10.0 5.0
4.0 31 36 0 2.5 5 7.5 10
0.0 0 1 2 3 4 5
Supply voltage :VCC[V]
VREG current : IVREG[mA]
VG current : IVG[mA]
Fig.4 Circuit current (BD6762FV)
Fig.5 VREG Voltage (BD6762FV)
Fig.6 VG Voltage (BD6762FV)
Power Dissipation Reduction
1200 1200
Power Dissipation : Pd mW)
Power Dissipation : Pd mW)
0 25 50 75 100 125 150
1100 1000 800 600 400 200 0 0 25 50 75 100 125 150
1000 950 800 600 400 200 0
Ambient Temperature: Ta( )
Ambient Temperature: Ta( )
Fig.7 BD6761FS Power Dissipation Reduction Reduced by 7.6 mW/C over 25C, when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm).
Fig.8 BD6762FV Power Dissipation Reduction Reduced by 8.8 mW/C over 25C, when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm)/
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5/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Block Diagram, Application Circuit Diagram, and Pin Function 1)BD6761FS
Technical Note
Output FET gate voltage stabilization resistor See P.19/22. Capacitor, diode for the protection between the output FET drain and source See P. 18/22.
0.1F CP1 BOOSTER TSD VG 1pin GND UVLO 32pin CP2 0.01F (0.01F ~ 0.1F) 0.1F
Capacitor for setting VG current capacity See P. 18/22. Capacitor for VCC pin noise elimination See P. 19/22. FGSOUT pull-up resistor See P. 20/22. Resistor for setting FG amplifier gain and the capacitor for the filter See P. 18/22. Capacitor for preventing VREG oscillation See P. 18/22.
UHG MOS FET ULG
REGURATOR 10.5V
VCC
10F
REGURATOR 10.5V FGSOUT
M
MOS FET VLG
LOGIC
VHG
PRE DRIVE
10k (1k ~ 100k) 470pF
FGOUT
R2 82k FGIN-
C2 1500pF
0.1F
R1 820 C1 470pF 0.47F 0.22F
WHG MOS FET MOS FET 0.1F WLG CURRENT LIMIT CL 1k RNF 0.033F (0.01F ~ 0.1F) PH 200 (200 ~ 1k) PEAK HOLD VCL2 S R Q Q EDGE DETECT TORQUE AMP OUTPUTOFF COMP
FGIN+
Resistor for setting the current limit See P. 18/22.
VREG
1k 0.1F (0.01F~0.1F) C3 R1 200(200 ~ 1k)
470pF 0.12
CPOUT
0.022 C4 0.33F R3 100k
CL voltage smoothing low pass filter See P. 18/22. Capacitor for setting the peak hold See P. 19/22.
RCP 100k
For setting Hall input level See P. 18/22.
R2
HU+
VCL1 CURRENT SENSE AMP CHARGE PUMP
ACC
HU
0.01F HUSLEW
Capacitor, resistor for setting the charge pump See P. 19/22.
DEC
Hall AMP
HV+
RATE DETECT
SHORT BRAKE
F/R
Capacitor for Hall noise elimination See P. 18/22.
0.01F HV HV-
0.1F CNF
Capacitor for setting the phase compensation See P. 19/22.
1000pF (500pF ~ 2000pF) HW+ 0.01F HW HW16pin TRAIANGLE WAVE GENERATOR RFE 17pin 50k (50k ~ 100k) CFE
External constant for setting PWM frequency See P. 18/22.
Fig.9 BD6761FS Block Diagram BD6761FS pin Function Pin Pin No. Function No. name name 1 GND GND pin 17 RFE 2 CP1 CP1 pin 18 CFE 3 UHG U-phase high-side FET gate pin 19 CNF 4 ULG U-phase low-side FET gate pin 20 F/R 5 VHG V-phase high-side FET gate pin 21 DEC 6 VLG V-phase low-side FET gate pin 22 ACC 7 WHG W-phase high-side FET gate pin 23 RCP 8 WLG W-phase low-side FET gate pin 24 CPOUT 9 CL Motor current detection pin 10 PH Peak hold pin 25 VREG Hall signal input pin 11 HU+ 26 FGIN+ Hall signal input pin 12 HU27 FGINHall signal input pin 13 HV+ 28 FGOUT Hall signal input pin 14 HV29 FGSOUT Hall signal input pin 15 HW+ 30 VCC Hall signal input pin 16 HW31 VG 32 CP2
Function CFE current control pin PWM frequency control pin Phase compensation pin Forward/reverse rotation switching pin Deceleration signal input pin Acceleration signal input pin CPOUT current control pin Charge pump output / Torque control signal input pin VREG pin FG input + pin FG input - pin FG output pin FGS output pin VCC pin Boost pin CP2 pin
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6/22
2010.06 - Rev.A
BD6761FS,BD6762FV
2)BD6762FV
RF voltage smoothing low pass filter See P. 18/22. Resistor for setting the current limit See P. 18/22. Capacitor for the protection between the output FET drain and source See P. 18/22.
UHG MOS FET VCO U LD ULG LP 0.1F VHG MOS FET VCO PRE V VLG DRIVER LOGIC R6 220k
INTIN
Technical Note
Capacitor for setting VG current capacity See P. 18/22.
BOOSTER CP1 0.01F (0.01F ~ 0.1F) RF 1k VG 0.1F VCC 1k ~ 100k LD 10k C7 0.22F (0.1F ~ 1F) LP CP2 10F
GND 470pF 0.1 RNF
CLK OSCILLATOR
Capacitor for VCC pin noise elimination See P. 19/22. Speed lock detection pull-up resistor
0.1F
M
INTOUT
C5 0.047F C6 0.47F
Capacitor for the motor lock detection time See P. 19/22. Integration amplifier external constant See P. 19/22. LPF external constant See P. 19/22.
DAC3 WHG MOS FET VCO W WLG (0.01F~0.1F) 0.1F VREG 1000pF (500pF ~ 2000pF) CFE
TRIANGULAR
R4 20k VELOCITY DISCRIMINATOR PLL DOUT
R5 1M
0.1F
MOS FET
Output FET gate voltage stabilization resistor See P. 19/22. Capacitor for preventing VREG oscillation See P. 18/22. PWM frequency external constant See P. 18/22. For setting Hall input level See P. 18/22. Capacitor for Hall noise elimination See P. 18/22. For setting Hall input level See P. 18/22.
R1
POUT C8 0.33F LPF
REGURATOR VCO
PHASE COMPARISON
C9 0.33F
CLKIN
R7 2k
OSCILLATOR
DIVIDER
FGSOUT
1k ~ 100k 10k
FGSOUT pull-up resistor
RFE 20k (20k ~ 100k)
R2
FGOUT
VCC 5k (2k ~ 10k)
390k FGINFGIN+
C2 150pF 4.7k 0.1F R1 C1
0.01F HU
HU+ HU-
1F
120/SL
Resistor for setting FG amplifier gain and the capacitor for the filter See P. 18/22.
0.01F HV
HV+ HV-
HALL COMP SB
FR 0.01F HW R2 HW+ HW2k (1k ~ 5k) ST/SP
Fig.10 BD6762FV Block Diagram BD6762FV pin Function No. Pin name Function No. Pin name 1 GND GND pin 21 ST/SP 2 RF Motor current detection pin 22 FR 3 UHG U-phase high-side FET gate pin 23 SB Protection pin for U-phase high-side 4 U 24 120/SL FET GS breakdown voltage 5 ULG U-phase low-side FET gate pin 25 FGIN+ 6 VHG V-phase high-side FET gate pin 26 FGINProtection pin for V-phase high-side 7 V 27 FGOUT FET GS breakdown voltage 8 VLG V-phase low-side FET gate pin 28 FGSOUT 9 WHG W-phase high-side FET gate pin 29 CLKIN Protection pin for W-phase high side 10 W 30 LPF FET GS breakdown voltage 11 WLG W-phase low-side FET gate pin 31 POUT 12 VREG Internal power supply 5 V output pin 32 DOUT 13 CFE PWM frequency control pin 33 INTIN 14 RFE CEF charge/discharge current control pin 34 INTOUT Hall signal input pin 15 HU+ 35 LP Hall signal input pin 16 HU36 LD Hall signal input pin 17 HV+ 37 VCC Hall signal input pin 18 HV38 VG Hall signal input pin 19 HW+ 39 CP2 Hall signal input pin 20 HW40 CP1
Function Start/Stop pin Forward/reverse rotation switching pin Short brake pin 120/slope switching pin FG amplifier input + pin FG amplifier input - pin FG amplifier output pin FGS output pin Reference CLK input pin VCO system loop filter connection pin PLL output pin Speed discriminator output pin Integration amplifier input pin Integration amplifier output pin Motor lock protection time setting pin Motor rotation number lock detection pin VCC pin Step-up voltage output pin Capacitor connection pin (to CP1) Capacitor connection pin (to CP2)
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7/22
2010.06 - Rev.A
BD6761FS,BD6762FV
I/O Logic 1)BD6761FS Forward rotation (F/R=Low) Input conditions Pin No. Condition 1 Condition 2 Condition 3 Condition 4 Condition 5 Condition 6 Condition 7 Condition 8 Condition 9 Condition 10 Condition 11 15 HU+ L L L L M H H H H H M 17 HV+ M H H H H H M L L L L 19 HW+ H H M L L L L L M H H H 3 UHG H H H H H PWM L L L L L PWM 5 VHG H PWM L L L L L PWM H H H H
Technical Note
Output state 7 WHG L L L PWM H H H H H PWM L L 4 ULG L L L L L PWM H H H H H PWM 6 VLG L PWM H H H H H PWM L L L L 8 WLG H H H PWM L L L L L PWM H H
Condition 12 L L Reverse rotation (F/R=High)
Input conditions Pin No.
Output state
15 HU+ L L L L M H H H H H M L
17 HV+ M H H H H H M L L L L L
19 HW+ H H M L L L L L M H H H
3 UHG L L L L L PWM H H H H H PWM
5 VHG L PWM H H H H H PWM L L L L
7 WHG H H H PWM L L L L L PWM H H
4 ULG H H H H H PWM L L L L L PWM
6 VLG H PWM L L L L L PWM H H H H
8 WLG L L L PWM H H H H H PWM L L
Condition 1 Condition 2 Condition 3 Condition 4 Condition 5 Condition 6 Condition 7 Condition 8 Condition 9 Condition 10 Condition 11 Condition 12
Input conditions Hall input voltage H: 3.05V M: 3.0V L: 2.95V
Output criteria High-side FET gate voltage L1V, VG-1VH Low-side FET gate voltage L1V, 9 VH
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8/22
2010.06 - Rev.A
BD6761FS,BD6762FV
ACC, DEC Input conditions 21 22 DEC ACC H H H L L L H L Output state 24 Short brake CPOUT OPEN OFF H L L OFF OFF ON
Technical Note
Pin No. Condition 1 Condition 2 Condition 3 Condition 4
Input conditions
ACC, DEC input conditions
H2.2V L0.8V Output criteria CPOUT RCP=13.5k, CPOUT=3V High: Current outflow more than 140A from CPOUT pin Low: Current inflow more than 140A to CPOUT pin OPEN: CPOUT pin current -10AICPOUT10A Short brake function On state High-side FET gate voltage1V Low-side FET gate voltage9V
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9/22
2010.06 - Rev.A
BD6761FS,BD6762FV
2)BD6762FV Forward rotation (F/R=Low), 120 (120/SL=High) Input conditions Pin No. Condition 1 Condition 2 Condition 3 Condition 4 Condition 5 Condition 6 15 HU+ L H H H L L 17 HV+ L L L H H H 19 HW+ H H L L L H High-side gate 3 6 9 UHG VHG WHG L H L L H L L L H L H H L L L H L L Output state Low-side gate 5 8 11 ULG VLG WLG L L H H L L H L L L L L H H L L L H
Technical Note
4 U M L L M H H
Output 7 V H H M L L M
10 W L M H H M L
Reverse rotation (F/R=High), 120 (120/SL=High) Input condition Pin No. Condition 1 Condition 2 Condition 3 Condition 4 Condition 5 Condition 6 ST/SP OPEN or High L Input condition
Hall input voltage H 2.0V M 1.5V L 1.0V M
15 HU+ L H H H L L
17 HV+ L L L H H H
19 HW+ H H L L L H
High-side gate 3 6 9 UHG VHG WHG L L H H L L H L L L H L L H L L L H
Output state Low-side gate 5 8 11 ULG VLG WLG L H L L H L L L H L L H H L L H L L
4 U M H H M L L
Output 7 V L L M H H M
10 W H M L L M H
Mode Standby Operating mode
HU-, HV-, HW-
Output criteria
High-side FET gate voltage Low-side FET gate voltage : Loutput (U, V, W) + 1V, VG - 1VH : L1V, 9VH
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10/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Timing Chart 1) BD6761FS
Hall signal
HU+ HUHV+ HVHWHW+ SINU SINV SINW Forward rotation UHG ULG VHG VLG WHG WLG Reverse rotation UHG ULG VHG VLG WHG WLG
Technical Note
Triangular waveform amplitude
Fig.11 BD6761FS I/O Timing Chart SINU, SINV, and SINW are the internal IC signals synthesized by the Hall amplifier.
2) BD6762FV
Hall signal
HU+ HUHVHV+ HWHW+ 120 UH UL VH VL WH WL 120 slope UH UL VH VL WH WL
Fig.12 BD6762FV I/O Timing Chart
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11/22
2010.06 - Rev.A
BD6761FS,BD6762FV
I/O Circuit Diagram 1) BD6761FS High-side gate
VG VG
Technical Note
Low-side gate
VREG 10.5V VCC
Hall input
VCC 5k HU+ (pin11) HV+ (pin13) HW+ (pin15) 5k HU- (pin12) HV- (pin14) HW- (pin16) VCC
100k
UHG (pin3) VHG (pin5) WHG (pin7)
2k
2k
ULG (pin4) VLG (pin6) WLG (pin8) 100k
Booster
VREG 8.5V VCC 30 CP1 (pin2) CP2 (pin32) VCC
CFE pin
VREG VREG
CPOUT pin
VREG 1k 5k VCC 30 CFE (pin18) 1k VCC 5k
VG (pin31)
1
CPOUT (pin24)
RCP, RFE pins
VREG 33k VCC 26k 30 RCP (pin23) 16k 30 RFE (pin17) VREG 44k VCC
ACC, DEC, FR pins
VCC VREG 5k ACC (pin22) DEC (pin21) F/R (pin20)
100k
Peak hold
VCC 200 200 PH (pin10)
Current sense amplifier
VREF VCC
Current limit
VREF 5k 5k 5k PH (pin10) 12k VCC 30 CNF (pin32) 5k VCC 5k PH (pin10) CL (pin9)
FG amplifier input
VREG VCC 25k FGIN+ (pin26) 200 200 FGIN(pin27) VCC
FG amplifier output
FGSOUT pin
VCC 30 30 3.1k VCC FGSOUT (pin29)
25k
FGOUT (pin28)
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12/22
2010.06 - Rev.A
BD6761FS,BD6762FV
2)BD6762FV RF pin
VCC
Technical Note
UHG, VHG, WHG, U, V, W pins
VG 1k VG UHG, VHG, WHG (pin3, 6, 9)
ULG, VLG, WLG pins
10.5V VCC
RF (pin2)
1k 80
70k 14k
VG U, V, W (pin4, 7, 10)
ULG, VLG, WLG (pin5, 8, 11)
CFE pin
VREG 5k 5k
RFE pin
VREG 100k
ST/SP, FR, SB, 120/SL
5V 5k 5k VCC 100k VCC
41k VCC 9k 30 5k 5k 5k 30 CFE (pin13) RFE (pin14) ST/SP(pin21) FR(pin22) SB(pin23) 120/SL(pin24)
5k
HU+, HV+, HW+, HU-, HV-, HW- pins
VREG VCC VREG VREG VCC
FGIN+, FGIN- pins
VREG VCC VREG VREG VCC
HU+(pin15) HV+(pin17) HW+(pin19)
5k
5k
HU-(pin16) HV-(pin18) HW-(pin20)
FGIN+ (pin25)
200
200
FGIN(pin26)
CLKIN
5V VCC 50k
FGIN+, FGOUT pins
VREG 30 30
15k
2.84k 200 5k 5k VCC
CLKIN (pin29)
5k
5k
200 VCC 15k
FGOUT (pin27)
FGIN+ (pin25)
FGSOUT pin
VREG
LPF pin
5V
POUT, DOUT pins
5V
VCC FGSOUT (pin28) 30 VCC POUT(pin31) DOUT(pin32) 30
30 30
1k
20k
LPF (pin30)
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13/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Technical Note
INTIN pin
VREG
INTOUT pin
VREG VCC 1k 90 5k VREG VREG
VCC INTOUT (pin34)
INTIN (pin33)
INTIN 90 1k INTOUT VREG 1k VREG
LP pin
VREG 5k 5k
LD pin
5V
LD(pin36) VCC 100k 5k 5k 5k 90 LP (pin35)
VG, CP2, CP1 pins
VCC VCC 8.5V
30 CP1 (pin40) CP2 (pin39)
30
VG (pin38)
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14/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Technical Note
IC Operation 1) Hall input and output For the hall input signal, the wave is shaped by the hall amplifier to generate the drive signal. This drive signal is amplified in the predriver block and the gate voltage is output for N-channel MOS FET. 2) PWM operation PWM oscillating frequency is determined by the triangular waveform frequency which is decided by the external constant. This triangular waveform voltage and the listed voltage in the following chart are compared to perform PWM drive. Cfe, CFE pin Frequency Rfe, RFE Cfe, CFE Comparison voltage charge/discharge current I (Typ.) Drive signal shaped by the BD6761FS 50k 1000pF 1.6V/R 16.5kHz hall amplifier Integration amplifier output BD6762FV 20k 1000pF VRFE/R 16kHz pin voltage Booster circuit (step-up circuit) (common) BD6761FS (Frequency = 62.5 kHz) and BD6762FV (Frequency = 125 kHz) generate the triangular waveform when the internal oscillator generates free-run oscillation and the rectangular waveform is generated at CP1. When a capacitor is connected between CP1 and CP2, and VG and GND, the step-up voltage is generated at VG pin. In this case, set VCC so that VG does not exceed the absolute maximum ratings (36 V). Triangular waveform oscillating Charge pump voltage (VG pin frequency voltage) BD6761FS 62.5 kHz VCC+6V BD6762FV 125 kHz VCC+6.7V FG amplifier (common) Set the FG amplifier gain so that the FGOUT pin is within the range of high and low output voltage and the amplitude is higher than the hysteresis width (250 mV: max) of the HYS amplifier. FGSOUT pin uses an open collector format. Use in the condition as it is pulled up to the power supply with the resistor. At this time, pay attention so that the voltage higher than 36 V is not applied to the FGSOUT pin. ACC, DEC circuits (BD6761FS) When a resistor is connected to the RCP pin and the low voltage is input to the ACC pin, the current flows out from the CPOUT pin. When the low signal is input to the DEC pin, the current flows in to the CPOUT pin. Furthermore, when the ACC pin and DEC pin both set to low, the current flows in to the CPOUT pin. This current can be converted to the voltage by connecting a filter between the CPOUT and GND pins. The voltage generated at the CPOUT pin controls the PWM's on-duty and maintains the constant motor rotation by inputting the controlled signal to ACC and DEC pins. Current limit operation When the CL voltage (BD6761FS) and RF voltage (BD6762FV) become the current limit voltage, the current limit circuit operates and works to limit PWM on_dutty. It also turns off the current limit circuit (current limit clear) at the peak of PWM triangular waveform and makes the current flow again. Output current Iomax at this time are shown in the table. Current limit current BA6761FS BA6762FV Iomax=0.48/RNF [A] Iomax=0.26/RNF [A]
3)
4)
5)
6)
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15/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Technical Note
7)
Output simultaneous on prevention circuit (BD6761FS, BD6762FV) When the low-side gate voltage becomes high while the high-side gate voltage is low, or when the high-side gate voltage becomes high while the low-side gate voltage is low, the simultaneous on prevention time is provided with t=3.2 s (TYP value). When the input capacity of external FET is C and the gate connection resistor is R, set R to satisfy the following equation so that the simultaneous on prevention time as mentioned above is not exceeded. 1.8 C 10 x( 24 + R )
Check that the simultaneous on is not made in the actual operation and then set C and R.
High-side gate
Low-side gate
t
t
t
t
t
t
Fig.13 High/Low-side Simultaneous On Prevention Timing Chart 8) Short brake (BD6761FS and BD6762FV) BD6761FS operates the short brake action with the ACC and DEC pins set to low, and BD6762FV does with the SB pin set to OPEN or high. At the time of short brake, the high-side gate is turned off and the low-side is turned on. At the time of short brake operating, the current flows to the output FET, which is decided by the motor's counter electromotive voltage and coil impedance. Since this current flows via path which does not run through the overcurrent protection (current limit) detection resistor, the overcurrent protection does not operate as IC operating. Therefore, the current more than the overcurrent protection set current may flow to the output FET, pay attention so that it does not exceed the output FET rating. Forward/reverse rotation circuit (BD6761FS and BD6762FV) Forward /reverse rotation of motor can be switched according to the FR pin input conditions. Logics of the hall input and output conditions according to the FR pin input conditions are shown in the I/O conditions table (P.10). If the FR pin is switched during the motor rotation, since the simultaneous on prevention circuit in IC operates, the feed through current does not flow. However, since the motor current flows in the direction to the power source due to the electromotive force, the voltage may be raised if the power source does not have the power supply voltage absorption ability. Examine the capacitor characteristics between the power supply and ground sufficiently and then pay attention so that the power supply voltage and step-up voltage do not exceed the absolute maximum ratings. When the physical measures are taken such as increasing the capacitor value which is connected between the power supply and ground, check the characteristics enough prior to use.
9)
10) Start/stop circuit (BD6762FV) When the ST/SP pin is in the sate of OPEN or high, IC becomes standby. In the case of standby, some circuits operation are turned off to reduce the current consumption. When the ST/SP pin is in the state of low, IC becomes operating. 11) Low voltage protection circuit (BD6761FS and BD6762FV) This IC builds in the low voltage protection circuit. When VCC becomes lower than 11.5 V (Typ.), the high-side and low-side gates are both turned off to make the coil turn off. Protection off voltage is 12.0 V (Typ.) and hysteresis width is 0.5 V (Typ.).Since the motor locking protection detection circuit operates in BD6762FV during the low voltage protection operation, if the low voltage protection operating time becomes longer than the motor locking protection detection time, the operation moves to the motor locking protection operation after the low voltage protection operation. 12) Built-in 120 slope PWM logic (BD6762FV) It is possible to perform 120 drive by setting 120/SL pin to OPEN or making high. 120 slope drive is possible by setting the 120/SL pin to OPEN or making high. Low noise design is realized by reducing the electromagnetic sound generated at the time of phase switching by means of gradually changing the output PWM on-duty during 120 slope energization. However, at the time of startup or the hall input frequency is lower than about 3 Hz (Typ. value), it becomes 120 drive. When the hall input frequency is more than about 3 Hz (Typ. value) and the rise of hall U-phase is detected 7 times, it switches to the 120 slope drive.
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16/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Technical Note
13) Servo circuit (BD6762FV) Frequency multiplication circuit (Dividing period) (BD6762FV) This IC builds in the frequency multiplication circuit. Servo circuit is composed of the feedback loop as shown in the diagram and flows in/out the current (22A: Typ.) to the LPF pin (30 pin) by detecting the phase difference between the CLKIN pin (29 pin) and the frequency dividing unit output FCOMP. The phase difference signal output to the LPF pin (30 pin) is smoothed by the filter which is connected at the IC external of the LPF pin (30 pin) and this voltage is input to the VCO (Voltage control oscillation circuit) to decide the frequency for the internal signal FVCO. Since the dividing ratio of this frequency dividing unit is set to 1024, the relation of FVCO[Hz]=1024FCOMP[Hz] can be obtained, and the FCOMP and CLKIN have the same frequency according to the feedback loop as shown in the following diagram, therefore the multiplied frequency of 1024 times of FCOMP or CLKIN is acquired as the FVCO frequency.
CLKIN Phase comparator Frequency dividing unit (1024 dividing) LPF
FCOMP
VCO (Voltage control oscillation circuit) FVCO
Speed discriminator (BD6762FV) The FGSOUT signal (28 pin) which detects the motor rotation speed and the reference clock in IC are compared and the acceleration/deceleration signal is output to the DOUT pin (32 pin). Reference clock is the signal (FVCO) that the CLKIN signal (29 pin) is multiplied by 1024. When the FG period is short to the reference clock period, it is determined that the motor revolution speed is too fast and the difference from the reference clock period is output to the DOUT pin as the deceleration command. When the FG period is long, the difference is output as an accelerating command. PLL (BD6762FV) Phases of the FGSOUT (28 pin) signal which detected the motor revolution speed and the CLKIN (29 pin) input from the external are compared, and if the FG phase leads to CLKIN (28 pin), the difference is output as the deceleration command. If the FG phase lags, the difference is output as the acceleration command. Integration amplifier (BD6762FV) Speed error of the reference clock which is obtained in the speed discriminator block and the FG signal, and the phase difference signal of the CLKIN acquired in PLL block and the FG are integrated together and smoothed to become the DC voltage. This smoothed signal determines the PWM on-duty. 14) Speed lock detection circuit (BD6762FV) When the motor speed is within 6.25% range to the CLKIN signal (29 pin), L is output to the LD pin (36 pin) output. Since the LD pin (36 pin) has the open/drain output format, use as it is pulled up to the power supply with the resistor (100k). At this time, pay attention so that the voltage more than 36 V is not applied to the LD pin. 15) Motor locking protection (BD6762FV) Motor locking protection circuit judges he motor is in the locking condition when the motor speed is not in the lock range (preset value: 6.25%) and the motor locking detection time TLP elapsed, the high-side and low-side output gates are both turned off.Motor locking protection can be cleared by making the condition Low after setting the ST/SP pin or the SB pin to OPEN or making high. Motor locking detection time TLP is determined by the capacitor C7 which is connected to the LP pin and the count number CLP (preset value: 96) of the internal counter.
TLP=2x10 xC7xCLP [S]
5
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17/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Selecting application components Design method Output FET This IC is the predriver for high-side and low-side N-channel MOS FET drive. Select the FET with the required current capacity to drive the motor. Diodes (BD67861FS) Diodes are required to protect between the gate and source of output FET. Protection capacitor between the output FET drain and source Check the operation so that the voltage between the output FET drain and source does not exceed the absolute maximum ratings due to the fluctuation of VCC at the time of PWM driving and then set the value. VB current capacitance capacitor Current capacity from VG changes according to the capacitance to be connected. However, if the capacitance is too large, the following action is delayed when VCC starts up, and the magnitude relation becomes VCC > VG which should be VCC < VG usually and the large current may flow in internal block circuits and result in damaging the circuits. When VG is directly supplied from the external block without using the internal circuits, disconnect the capacitor between CP1 and CP2, and connect the 20k resistor (for noise reduction) between CP1 and ground to use. PWM frequency PWM frequency can be adjusted by the capacitance and resistance to connect. When the frequency is high, the heat generation increases due to switching loss. When the frequency is low, it enters audible range. Check the operation with the actual product and determine the constant. Hall input level The current value to feed to the hall element changes by changing the resistance and the amplitude level of hall element can be adjusted. Amplitude level increases when the resistance value is chosen smaller by considering the noise affect, but pay attention also to the hall input voltage range. BD6761FS (1.5V to 4.1V) and BD6762FV (0V to 3V) VREG VREG which is the internal voltage output pin drives the circuits in IC. Connect the capacitor to stabilize it. Current limit The current flowing to FET can be controlled by setting the resistance value. Determine the constant according to the motor specifications. Hall input noise Insert capacitors between the hall phases in order to eliminate the hall input noise due to the effect by the pattern routing design. CL (RF) voltage smoothing low pass filter Smooth the CL (RF) voltage which has PWM noise through the low pass filter.
Technical Note
Design example Recommended FET RDS035L03 (A)
Recommended diode 1SS355 Insert the diode in the direction from high-side FET source to the gate side (in the forward direction). A value of 0.01 to 0.1F is recommended. A value of 0.1F is appropriate for the capacitance. Insert the capacitor between the output FET drain and source. (Position at the close point to FET as much as possible.) A value of 0.01F is appropriate for the capacitor between CP1 and CP2 (A value of 0.01F 0.1F is recommended.) A value of 0.1F is appropriate for the capacitor between VG and VCC.
The following constants are appropriate. BD6761FS Cfe=1000pF, Rfe=50k, fo=16.5kHz(TYP.) BD6762FV Cfe=1000pF, Rfe=20k, fo=16.0kHz(TYP.) Connect to the transistor base via 1k resistor (base current limit) from the VREG pin. Connect the transistor collector to VCC, the emitter to the hall element via R1. Connect the ground side of hall element to the ground via R2. A value of 200 to 1k is recommended. A value of 200 is appropriate, respectively. When connecting to the VCC side directly with R1, values of R1=5k and R2=2k are appropriate. A value of 0.01F to 0.1F is recommended. A value of 0.1 is appropriate. Following equation shows the current value. BD6761FS Iomax=0.48/RNF [A] BD6762FV Iomax=0.26/RNF [A] A value of 0.01F is appropriate for the capacitor to be installed between the hall phases. A value of 0.01F to 0.1F is recommended. A value of C = 470pF and R=1k is appropriate for the low pass filter. For the external constant, since the impedance is high, make sure to design the pattern with the shortest circuit route so that the circuit is hard to be affected by noise. R1 and C1 form a high pass filter and R2 and C2 form a low pass filter. Each cut off frequency; fMPF and fLPF is determined by the following equation. fMPF=1/2R1C1, fLPF=1/2R2C2 Set the value so that the main signal from PG by the motor is not attenuated but the unnecessary noise can be attenuated.
FG AMP constant setting FG AMP gain: GFG is the ratio of R1 and R2 calculated by the following equation. GFG=20log R2/R1 [dB] Set up the gain so that the FGOUT amplitude is large enough to the hysteresis level of the hysteresis comparator and it cannot be clamped by the high and low output voltages (VFGOH and VFGOL).
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18/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Technical Note
Design method Phase compensation capacitor (BD6761FS) Phase compensation is performed in the output of the CS amplifier. The capacitance value should be selected according to the servo constant, and proper motor operation should be confirmed. When the capacitance is large, the I/O response becomes bad. When it is small, the output becomes easy to oscillate. VCC pin Set up the capacitance for the stabilization and noise reduction on the power line. Charge pump filter(BD6761FS) Filter composed of C3, C4 and R3 smoothes the current pulses output from the CPOUT pin and converts it to DC. This impedance Z is shown by the following equation. S+2 C4 x Z = R3x S C3+C4 S 1+ 1 When the pole frequency is set to fP1 and fP2, they are: fP1=1/2=1/2(C3//C4)R3 fP2=2/2=1/2C4R3 Output FET gate voltage stabilization resistor When the noise is generated at the time of external MOSFET on/off due to the rise and fall speed of the IC output, insert the resistor between the IC output and external MOSFET gate. Peak hold setting capacitor (BD6761FS) Charges the peak hold on the voltage at the current detection pin CL. Motor locking detection time setting capacitor (BD6762FV) Motor locking detection time TLP is determined by the capacitor C7 which is connected to the LP pin and the count number CLP (Preset value: 96) of the internal counter. The TLP is shown by the following equation. 5 TLP=2x10 xC7x96 Integration amplifier constant setting (BD6762FV) Speed discriminator side current value ID is shown by|ID|=2.5/R4 and the PLL side current value IP is shown by|IP|=2.5/R5. Therefore, the current IIN which flows in the integration AMP input pin INTIN is shown by IIN=ID+IP. The larger the IIN is, the higher the integration amplifier gain becomes. Gains of the speed discriminator and PLL can be set by adjusting R4 and R5. Gain G is shown by the following equation. G= R6 R4 // R5 x C6 C5+C6 x S S+2 S 1+ 1
Design example A value of 0.001F to 0.1F is recommended. A value of 0.001F is appropriate for BA6680FS. A value of 0.1F is appropriate for BD6761FS.
A value of value 1F to 10F is recommended. A value of 10F is appropriate. Recommended value C3: 0.01F to 0.1F; a value of 0.01F is appropriate. C4: 0.033F to 0.33F; a value of 0.1F is appropriate. R3 : 30k to 300k; a value of 100k is appropriate.
Establish R so that the simultaneous on prevention time is not exceeded as shown in 7). Output simultaneous on prevention circuit in P.17/24 Operating Explanation. A value of R = 0 is appropriate. A value of 0.33F is appropriate.
A value of 0.22F is appropriate.
Recommended value R4: 10k to 40k; a value of 20 k is appropriate. R5: 300k to 3M; a value of 1 M is appropriate. R6: 100k to 500k; a value of 220 k is appropriate. C5: 0.01F to 0.1F; a value of 0.047F is appropriate. C6: 0.033F to 1.0F; a value of 0.47F is appropriate.
When the pole frequency is set to fP1 and fP2, they are: fP1=1/2=1/2(C5//C6)xR6 fP2=2/2=1/2C6R6 LPF external constant (BD6762FV) Filter composed of C8, C9 and R7 smoothes the current pulses output from the LPF pin and converts it to DC. This impedance Z is shown by the following equation. Z = R7x C9 C8+C9 x S S+2 S 1+ 1
Recommended value C8: 0.1F to 0.6F; a value of 0.33F is appropriate. C9: 0.1F to 0.6F; a value of 0.33F is appropriate. R7: 0.5k to 10k; a value of 2k is appropriate.
When the pole frequency is set to fP1 and fP2, they are: fP2=2/2=1/2C9R7 fP1=1/2=1/2(C8//C9)R7
Setting values in these materials are only for reference. Actual set may change its characteristics due to the boards layout, wiring and components type to use. Please perform the sufficient verification using the actual product for the field operation.
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19/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Technical Note
Notes for use (1) Absolute maximum ratings This product is subject to a strict quality management regime during its manufacture. Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. (2) Connecting the power supply connector backward Connecting the power supply connector backwards may result in damage to the IC. For the protection of the IC from reversed connections, provide an appropriate measure, such as the insertion of an external diode each between the power supply and the power supply pin of the IC and between the motor coils. Power supply lines The regenerated current resulting from the back EMF of the motor will return. Therefore, take an appropriate measure, such as the insertion of a capacitor between the power supply and GND. Determine the capacitance in full consideration of all the characteristics of the electrolytic capacitor, because the electrolytic capacitor may loose some capacitance at low temperatures. If the connected power supply does not have sufficient current absorption capacity, regenerative current will cause the voltage on the power supply line to rise, which combined with the product and its peripheral circuitry may exceed the absolute maximum ratings. It is recommended to implement a physical safety measure such as the insertion of a voltage clamp diode between the power supply and GND pins. GND potential Ensure a minimum GND pin potential in all operating conditions. Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. Pin shorts and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. Thermal shutdown circuit (TSD) This IC incorporates a TSD circuit. If the chip becomes the following temperature, coil output to the motor will be open. The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the TSD circuit is assumed. TSD on temperature [C] (Typ.) 175 175 Hysteresis temperature [C] (Typ.) 35 23
(3)
(4)
(5)
(6)
(7)
(8)
(9)
BD6761FS BD6762FV
(10) PWM drive Voltage between the output FET drain and source may exceed the absolute maximum ratings due to the fluctuation of VCC at the time of PWM driving. If there is the threat of this problem, it is recommended to take physical countermeasures for safety such as inserting the capacitor between the VCC pin of FET and the detection resistor pin. (11) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process.
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20/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Technical Note
(12) Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in Fig. 14, the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (P substrate) voltage to input pins.
Resistor Pin A Pin A
P
+
Transistor (NPN) Pin B
C B E B P P+ N C E
Pin B
N P
N
P+
N
Parasitic element
N
P
+
N
P substrate Parasitic element
GND
P substrate Parasitic element
GND GND GND
Parasitic element
Other adjacent elements
Fig. 14 Mimetic Diagram of Parasitic Element (13) Ground Circuit Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external parts, either.
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21/22
2010.06 - Rev.A
BD6761FS,BD6762FV
Ordering part number
Technical Note
B
D
6
Part No. 6761 6762
7
6
1
F
S
-
E
2
Part No.
Package FS : SSOP-A32 FV : SSOP-B40
Packaging and forming specification E2: Embossed tape and reel
SSOP-A32

13.6 0.2 (MAX 13.95 include BURR)
32 17
Tape Quantity Direction of feed
0.3MIN
Embossed carrier tape 2000pcs E2
The direction is the 1pin of product is at the upper left when you hold
7.80.3
5.40.2
( reel on the left hand and you pull out the tape on the right hand
)
1
16
1.80.1
0.15 0.1
0.11
0.36 0.1 0.8
0.1
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
SSOP-B40

13.6 0.2 (MAX 13.95 include BURR)
Tape Quantity
21
Embossed carrier tape 2000pcs E2
The direction is the 1pin of product is at the upper left when you hold
40
7.8 0.3
5.4 0.2
1
20
1.8 0.1
0.15 0.1
0.1
0.1 0.65 0.22 0.1 0.08
M
S
0.5 0.2
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
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22/22
2010.06 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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